1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device including evaluation elements which is capable of specifying a failure location in nondestructive manner.
2. Description of the Prior Art
Conventionally, evaluation of electrical properties, quality, reliability, and the like of a semiconductor device has been conducted by forming a chain through serial connection of such elements as metal wirings and via-holes (vias for short) which is connected to an external measurement instrument by means of a probing or a wire bonding provided at both ends of the chain, and evaluating the electrical characteristics of the device using the external measurement instrument.
For example, in a reliability evaluation element shown in FIG. 2 and a via yield evaluation element shown in FIG. 4, an element is given a configuration in which a chain is formed by alternately connecting a metal wiring composed of a first layer 1 and a metal wiring composed of a second layer 2 by means of a via 3, connecting both ends of the chain to respective pads, and connecting the chain to an external measurement instrument from the pads through a probing or a wire bonding. With such a configuration, when an abnormality of wire breakage occurs in any one of the metal wirings or the vias 3, a disconnection will be observed as an electrical characteristic.
In general, as the methods of evaluating quality and reliability of a semiconductor device, there have been known nondestructive failure analysis techniques, such as the liquid crystal method which detects a locally heated location due to a current by utilizing birefringency of liquid crystals, the thermography which detects a heated location by using infrared rays, and the optical beam induced resistance change (OBIRCH) method and the non-bias optical beam induced current (NB-OBIC) method which measure a change in the current induced by laser beams, in addition to the appearance inspection and evaluation of electrical characteristics. Although the location where abnormality occurred can be specified by the methods just enumerated, when a disconnection is observed by the electrical characteristic evaluation using the conventional evaluation circuit described in the above, there has been a problem in that specification of abnormality location using nondestructive failure analysis methods such as the liquid crystal method, thermography, the OBIRCH method, the NB-OBIC method, and the like which require electrical measurement are invalid due to the loss of electrical connection to begin with.
Under these circumstances, the abnormality location is specified by employing a semi-destructive analysis method such as the potential contrast method that involves an observation by scanning electron microscopy (SEM) or a focused ion beam (FIB), so that it is necessary to remove all the covering films over the layer to be observed and hold the sample in a vacuum, which leads to a problem in that a complicated processing is required for the machining and the observation.
As described in the above, availability of almost all of the conventional evaluation circuits, which is so configured that all the elements are connected in series in order to maximize the detection sensitivity of abnormality of electrical characteristics, is invalidated due to the fact that the electrical connection is lost when an abnormality is observed under the circumstance that the nondestructive failure analysis often requires measurement of the electrical characteristics for the specification of abnormality location. It should be mentioned that a technique relevant to the present situation has been disclosed in J. of Appl. Phys., Vol. 90, No. 2, p. 732 (2001). However, the method is not regulating the wiring spacing (uses the minimum spacing in general), and is not presupposing its application to nondestructive failure analysis, so that it is of no help in solving the above problem.
In a semiconductor device including evaluation elements configured by a plurality of first wirings composed of a first wiring layer, a plurality of second wirings composed of second wiring layer and vias which connect the first wirings and the second wirings, the first wirings and the second wirings are formed in directions almost perpendicular with each other, a plurality of the second wirings that connect adjacent first wirings are juxtaposed in the length direction of the first wirings, with respect to the plurality of first wirings juxtaposed with a prescribed interval, to form a plurality of current paths in parallel.